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![PDF] Study and Verification on the Latch-Up Path Between I/O pMOS and N-Type Decoupling Capacitors in 0.18- $\mu$ m CMOS Technology | Semantic Scholar](https://d3i71xaburhd42.cloudfront.net/25a1c700fc1d6cb210015f31c1dcb1d4a333eaef/1-Figure1-1.png "PDF] Study and Verification on the Latch-Up Path Between I/O pMOS and N-Type Decoupling Capacitors in 0.18- $\mu$ m CMOS Technology | Semantic Scholar")
PDF] Study and Verification on the Latch-Up Path Between I/O pMOS and N-Type Decoupling Capacitors in 0.18- $\mu$ m CMOS Technology | Semantic Scholar
Figure 2 from Latch-up characterization and checking of a 55 nm CMOS mixed voltage design | Semantic Scholar
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Latch-up - Wikipedia
Study and Verification on the Latch-Up Path Between I/O pMOS and N-Type Decoupling Capacitors in 0.18-<inline-formula> <
Latch-up
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